1. Field of the Invention:
The present invention relates generally to semiconductor integrated circuits, and more specifically to a circuit for generating a signal indicative of the initial application of power to an integrated circuit.
2. Description of the Prior Art:
For many integrated circuits, it is important that the circuitry on the chip power-up in a known state. This is true of sequential circuitry such as programmable logic devices having registers, microprocessors, and controllers. Failure to power up in a predictable state can cause such an integrated circuit to fail to function.
One technique for ensuring that an integrated circuit chip powers up in a known state is to provide a circuit on the chip which senses the initial application of power to the chip, and generates a reset signal which is applied to all registers on the chip. Such circuits are typically referred to as power-up reset circuits. The circuitry must ensure that the reset signal is applied after the supply voltage is high enough to ensure that all on chip logic is operating in a stable manner. The reset signal can be applied after the supply voltage has risen to a predetermined, minimum level, or it may be applied earlier and held until after the supply voltage has risen high enough to ensure stable circuit operation on the chip.
CMOS circuits become stable when the supply voltage is greater than the sum of the absolute values of the threshold voltages of the P-channel and N-channel devices. Thus, the power-up reset signal must be held until V.sub.cc &gt;.vertline.V.sub.TN .vertline.+.vertline.V.sub.TP .vertline.. The power-up reset circuitry must ensure that the reset signal is delayed until all parts of the chip have reached a stable operating voltage.
A typical power-up reset circuit used in the prior art is shown in FIG. 1. In such a circuit 10, a resistor 12 is connected to the positive voltage supply V.sub.cc and a capacitor 14. As is known in the art, a CMOS capacitor is easily fabricated using the gate oxide layer as the capacitor dielectric, with the source and drain grounded. The other side of the capacitor 14 is connected to ground.
A common node 16 between the resistor 12 and capacitor 14 is connected to the input of an inverter 18. The inverter 18 comprises a P-channel transistor 20 and an N-channel transistor 22 in the standard configuration. Output node 24 of the inverter 18 generates the signal PUPRST, which is the power-up reset signal for the remainder of the circuitry on the integrated circuit chip.
Upon power-up, once V.sub.cc rises above .vertline.V.sub.TP .vertline., the signal PUPRST tracks V.sub.cc. Thus, PUPRST rises as V.sub.cc rises. This logical high signal causes an asynchronous reset on all of the registers on the chip. Individual flip flops containing chip state information are also preferably reset by this signal.
As V.sub.cc rises, current through the resistor 12 charges the capacitor 14 and raises the voltage at node 16. As the voltage on node 16 rises to a logic high level, the action of the inverter 18 causes the voltage at node 24 to go low. The signal PUPRST will remain low for as long as power is supplied to the chip.
The values for the resistor 12 and capacitor 14 are chosen so that the resulting RC time constant is greater than the specified minimum rise time for V.sub.cc. The sizes of transistors 20 and 22 are chosen so that the combination of the trip point of the inverter 18 and the RC time constant allow PUPRST to be asserted for a sufficient time after V.sub.cc rises above.vertline.V.sub.TN .vertline.+.vertline.V.sub.TP .vertline..
The length of time for which the signal PUPRST is asserted is therefore dependent upon process variations which occur during fabrication of the resistor 12, capacitor 14, and transistors 20,22. The desired minimum delay during which PUPRST is asserted, necessary in order to assure that all circuits on the chip have reached stable operating voltages, can therefore be compromised due to variations in the chip fabrication process. This means that the power-up reset circuitry 10 must be nominally designed for a long delay, or the chip may not power up in a known state. Selection of an inverter trip point which is too high or an RC time constant which is too long may extend the reset cycle so far that a system tries to access the chip before reset is complete.
It would therefore be desirable to provide a power-up reset circuit which reliably delays the reset signal until the supply voltage is high enough to ensure stable operation of the chip circuitry. It would further be desirable to provide such a circuit which operates properly even when process variations impact the operating parameters of chip circuitry.